1. Field of the Invention
The present invention relates to a semiconductor memory device, e.g. a semiconductor memory device in which a memory cell includes a ferroelectric material.
2. Description of the Related Art
Ferroelectric memories are known in which a memory capacitor includes a ferroelectric material. Some of them are TC-parallel-unit series connection type ferroelectric memories. These memories have a structure in which a plurality of unit cells are electrically connected in series, the unit cell comprising a cell transistor (T) in which opposite ends of a capacitor (C) are connected between the source and drain of the transistor.
FIG. 21 is a sectional view schematically showing a TC-parallel-unit series connection type ferroelectric memory (hereinafter simply referred to as a “semiconductor memory device” unless otherwise specified). As shown in FIG. 21, memory cell transistors 104 each composed of a gate electrode 102 and source/drain diffusion areas 103a, 103b are formed on a surface of a semiconductor substrate 101. A memory cell capacitor 114 composed of a lower electrode 111, a ferroelectric film 112, and an upper electrode 113 is formed above the transistor 104.
The lower electrode 111 is connected to the source/drain diffusion area 103a by a contact 121. The upper electrode 113 is connected to the source/drain diffusion area 103b via a connection layer 122, a plate electrode 123, and a contact 124. One of the memory cell transistors 104 is connected to a select transistor 131. A source/drain diffusion area 103a of the select transistor 131 is connected to a bit line 133 via a contact 132.
Further, the structure shown in FIG. 22 is known as a ferroelectric memory having a structure different from the TC-parallel-unit series connection type. In the ferroelectric memory of this structure, the source/drain diffusion area 103b shared by the two transistors 104 is connected to a bit line 133 via the contact 132. The upper electrode 113 and the plate electrode 123 constitute a single electrode extending in a direction perpendicular to the sheet of the drawing.
To reduce the size of a semiconductor memory device while increasing its density, it is desirable to reduce an area per unit cell. For the semiconductor memory devices shown in FIGS. 21 and 22, the area per unit cell has been reduced by scaling down a design rule.
Thus, the more the area per unit cell shrinks, the more the gate length of a transistor decreases. However, too small a gate length may result in a short channel effect. The short channel effect may cause the memory cell transistor to malfunction. Thus, with the structures shown in FIGS. 21 and 22, the reduction in the area per unit cell is limited.
Further, the more the area per unit cell shrinks, the higher the aspect ratios of the contacts 121, 124, and 132 become. With high aspect ratios, when the contact 121, 124, and 132 are formed, the corresponding contact holes may not be sufficiently filled with a conductive material. As a result, inappropriate contacts may occur. Further, it is difficult to form the contact holes themselves.